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20260226 - Fauna Lock In Amp Rescue

The tasks would be:

  • Rescue the work that was done on the Lock In Amplifier
  • Make it to work on a FPGA

Tasks:

  • Run simulations and test scripts, confirm integrity [4 hours]
  • Design HDL architecture
    • Define the signals [2h]
    • Define the filters [2h]
    • Define the data flow [2h]
  • Implement SPI receiver implementation for new ADC [12h]
    • Simulation
    • Implementation
    • Testing on hardware
  • Implement SPI transmitter implementation [12h]
  • Create example SIN + SPI transmitter [2h]
  • Create example LockIn + Filter [6h]
  • Create the full design with 2 frequencies and all filters [12h]
    • We dont know yet if is going to be with the final PCB
  • Test with real hardware [6h]
  • Generate documentation [4h]

Total of hours: 64h Working hours + 16h Meeting hours (1/4th)

Price per hour: 700 DKK Hour

I can compromise for 4/6 hours a week of work

Equipment needed:

Questions:

  • Which ADC?
  • Which requirements for filters?

Offer

CVR: 444479060 Company name: Insight Sat Client company name: evolito A/S Title: Lock In amplifier design using FPGA technology Date: 3 March 2026 Version number: 1

Vocabulary:

  • Client: evoluto A/S

Executive summary: The client needs to design a FPGA architecture for processing two electrical signals using algorithms of Digital Signal Processing. The nature of the signals are low gain, centred around 80KHz with high noise environment. The objective is to filter the signals using a Lock In amplifier developed on a FPGA.

Some previous documentation and VHDL IPs are provided by the client. Part of the project would be to update them and verify their functionality.

The duration of the project is 10 weeks divided in 3 phases, with milestones in each of them.

The phases of the project are:

  1. Phase 1:
    1. Describe the requirements of the system. Define the input signals, the filters that are going to be used, the data flow diagram, and the output signals.
    2. Design VHDL and testbench implementation for ADC driver. MISSING THE ADC
    3. Design VHDL and testbench implementation for Slave SPI driver. DONE, missing documentation
    4. Adapt from previous work the VDHL and testbench implementation for Sine generator DONE
    5. Adapt from previous work the VDHL and testbench implementation for CIC decimator. DONE
    6. Adapt from previous work the VHDL and testbench implementation for FIR filter. DONE
    7. Adapt from previous work the VHDL and testbench implementation for signal mixer. DONE
  2. Phase 2:
    1. Hardware implementation validating the Slave SPI driver. DONE
    2. Hardware implementation validating the ADC driver.
    3. Hardware implementation validating the Sine generator driver. DONE
    4. Hardware implementation validating the CIC filter
    5. Hardware implementation validating the FIR filter
  3. Phase 3:
    1. Design VHDL and testbench implementation for Lock In amplifier
    2. Hardware implementation validating the Lock in amplifier

The project is going to be billed hourly, for 700DKK/Hour. Estimated work is 70Hours without meetings. For each opening and closing of phase is planned a meeting of 2h. Resulting in a total of 82Hours.


Meeting 3 March

Points of the meeting:

  • Discuss the draft DONE
    • Add address.
    • Remove is a draft
    • Invoicing should be done after each phase.
    • Put hours for each phase
    • Put a start date on each phase
  • Change email
  • Fauna needs to send the NDA, after the offer is signed, and the requirements. Then I will request a meeting if necessary. I can propose an ADC to work on.
  • Send fauna list of equipment DONE