The way to upload code with the PYNQ board is really specific. It is necessary to generate a overlay.

Sources:

• Creating a custom IP block in Vivado using AXI interphace
• Creating a custom AXI-Streaming IP in Vivado
• Specification of AXI Stream interface
• Example video to create a custom AXI Stream IP with vivado
• 20220905 - Hardware FIR Filter on Pynq Board

The steps are the next ones:

• Create Block Design
• Place ZYNQ processing system
• Go to ZYNQ module, click in hich performance axi, enable the S AXI HP0
• Run automation
• Place DMA and your rtl code. In the options of DMA deactivate “Enable Scatter Gather Engine”, put the Width of Buffer to 23. Interconnect the master with the slave, the slave with the master
• Run automation
• Rename the modules to make them easier to reference in the future, create a hierichal block with the dma and the filter
• Click on the design, generate HDL wrapper
• Generate bitstream