Download radiant: 20230314 - iCEbreaker with Radiant
Make sure you have added the license, and configured the environment variable.
Open radiant, create a project, add the next sources counter.vhd:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic (
WIDTH : positive := 8
);
port (
clk : in std_logic;
rst_n : in std_logic; -- active-low reset
en : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end entity;
architecture rtl of counter is
signal cnt : unsigned(WIDTH-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
cnt <= (others => '0');
elsif en = '1' then
cnt <= cnt + 1;
end if;
end if;
end process;
q <= std_logic_vector(cnt);
end architecture;
And create another one called tb_counter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_counter is
end entity;
architecture sim of tb_counter is
constant WIDTH : positive := 8;
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal en : std_logic := '0';
signal q : std_logic_vector(WIDTH-1 downto 0);
begin
-- DUT
dut: entity work.counter
generic map ( WIDTH => WIDTH )
port map (
clk => clk,
rst_n => rst_n,
en => en,
q => q
);
-- 100 MHz clock (10 ns period)
clk <= not clk after 5 ns;
-- Stimulus
process
begin
-- hold reset low briefly
rst_n <= '0';
en <= '0';
wait for 50 ns;
-- release reset
rst_n <= '1';
wait for 20 ns;
-- enable counting
en <= '1';
wait for 200 ns;
-- pause counting
en <= '0';
wait for 50 ns;
-- count again
en <= '1';
wait for 100 ns;
-- done
assert false report "Simulation finished" severity failure;
end process;
end architecture;
Add the two sources, and then configure the simulation wizard. Select the correct top part.