In this note I will write what I am learning about hte iCEBreaker PCB:

• First Steps with the iCEBreaker FPGA Development Board

Example project using iCEcube2

After some hours I manages to make the iceBreaker FPGA works, here I am going to explain how I did it:

• Install iCEcube2 using docker, 20230131 - iceCube2 on a Dockerfile
• Open iceCube2 and open preferences -> Bitmap and mark “Set all unused IO no pullup”.
• Create a project and the properties are:

• Synthesis Tool Right click and Select Synthesis Tool to Lattice LSE.
• Design Files -> Add files and add a file with the next content:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity main is
  port (
    i_clock : in std_logic;
    o_led : out std_logic;
    i_button : in std_logic;
    o_otherled : out std_logic
  ) ;
end entity main;

architecture arch of main is

    constant CLOCK_FREQUENCY : integer := 12000000; -- input clock frequency (12 MHz)
    signal counter : unsigned(31 downto 0) := (others => '0'); -- 32-bit counter to measure 1 second
    signal r_led : std_logic := '0';
begin

    PROC_LIGHT : process( i_clock )
    begin
        if rising_edge(i_clock) then -- detect rising edge of input clock
                counter <= counter + 1; -- increment counter on each clock cycle
                if counter = to_unsigned(CLOCK_FREQUENCY, counter'length) then -- check if counter reaches 1 second
                    r_led <= not r_led; -- toggle the LED on and off
                    counter <= (others => '0'); -- reset the counter to start again
                end if;
            end if; 
    end process ; -- PROC_LIGHT
  
  o_otherled <= i_button;
  o_led <= r_led;

end arch ; -- arch

• It is necessary to create the clock constraint in the Synthesis with the following information. This step is necessary because the code is going to be optimized for that frequency:

create_clock -period 83.3333 -name clk12Mhz [get_ports i_clk]

• Then Run Lattice LSE Synthesis
• Import P&R Input Files
• Tools -> Pin Constraints Editor and add the next configuration:

• The last pin location used is the next one:

• Then Run P&R
• Go to Getting_started_iCEBreaker/Getting_started_iCEBreaker_Implmnt/sbt/outputs/bitmap] and run the next command iceprog main_bitmap.bin