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20221201 - VHDL - Skeleton proccess

This is a sample code of a small application that uses inputs and outputs:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity main is
  port (
    i_clock : in std_logic;
    o_led : out std_logic;
    i_rst : in std_logic
  ) ;
end entity main;

architecture arch of main is

    constant CLOCK_FREQUENCY : integer := 12000000; -- input clock frequency (12 MHz)
    
	signal counter : unsigned(31 downto 0); -- 32-bit counter to measure 1 second
    signal r_led : std_logic;
begin

    PROC_LIGHT : process( i_clock )
    begin
		if rising_edge(i_clock) then -- detect rising edge of input clock
			if (i_rst='1') then
				counter <= (others => '0');
				r_led <= '0';
			else
                counter <= counter + 1; -- increment counter on each clock cycle
                if counter = to_unsigned(CLOCK_FREQUENCY, counter'length) then -- check if counter reaches 1 second
                    r_led <= not r_led; -- toggle the LED on and off
                    counter <= (others => '0'); -- reset the counter to start again
                end if;
            end if;
		end if;
    end process ; -- PROC_LIGHT
  
  o_led <= r_led;

end arch ; -- arch