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20220816 - VHDL Generate

It helps to generate automated code. Here is an example, remind that [ ] refer to optional arguments.

label : for parameter in range generate

[ { declarations } ]

begin

{ concurrent_statements }

end generate [ label ] ;

Or:

label : if condition generate

    \[ { declarations }

  begin \]

    { concurrent_statements }

end generate \[ label \] ;

As an example, it could be like:

g_adc: for adc in 0 to NUM_ADCS-1 generate
      constant AWID     : natural := ADC_BUF_AWID;
      signal buf_wen    : std_logic;
      signal clk_diven  : std_logic := '1';
      signal buf_wdata  : std_logic_vector(DWID-1 downto 0) ;
      signal buf_waddr  : unsigned(AWID-1 downto 0) := (others => '0');
      signal buf_raddr  : unsigned(AWID-1 downto 0) := (others => '0');
      signal buf_rdata  : std_logic_vector(DWID-1 downto 0) ;
      signal buf_ren    : std_logic;
   begin
      buf_wen    <= (tick_2mhz and clk_diven) when (signed(buf_waddr) /= -1) else '0';
      
         -- write ADC values
      buf_wdata  <= std_logic_vector(adc_data(adc)(DWID-1 downto 2) & dac_a_tmp & dac_b_tmp) when cfg_adc_cnt_en='0'      
         -- write counting values to buffer
         else    std_logic_vector(resize( buf_waddr, adc_data(0)'length));
end generate;