RF VCO Frecuency equation:
RFOUT=fPFD⋅(INT+(FRAC/MOD))
The PFD frequency (\(\f_{PFD})) equation is:
fPFD=REFIN⋅[(1+D)(R⋅(1+T))]
Donde:
- REFIN is the reference input frequency
- D is the REFIN doubler bit (0 or 1).
- R is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023).
- T is the REFIN divide-by-2 bit (0 or 1).
Voy a coger de ejemplo el registro de 1 GHz con 10 MHz de reloj 0xC80000, 0x8008321, 0x4E42, 0x4B3, 0xA503FC, 0x580005
Regiter 0:
- Control bits: 0
- 12-Bit fractional value: FRAC = 0
- 16-bit integer value: INT = 400
0 0000000110010000 000000000000 000
0000 0000 1100 1000 0000 0000 0000 0000
Register 1:
- Control bits: 0b001
- 12-bit modulus value: MOD = 100
- 12-bit phase value: PHASE = 0b1 -> RECOMMENDED
- PRESCALER: 0b1 -> 8/9
- PHASE ADJUST: 0b0 -> OFF
- Reserved
000 0 1 000000000001 000001100100 001
0000 1000 0000 0000 1000 0011 0010 0001
Register 2:
- Control bits: 0b010
- Low noise and low spurs modes: 0b00 LOW NOISE MODE
- Muxout: 0b000 THREE-STATE OUTPUT
- Reference Doubler: 0b0 DISABLED
- RDIV2: 0b0 DISABLED
- 10-Bit R counter: 0b1 -> R COUNTER = 1
- Double Buffer: 0b0 DISABLED
- Charge Pump Current Setting -> 0b0111 -> I_CP [mA] = 2.5
- Lock Detect Function (LDF): 0b0 -> FRAC-N
- Lock Detect Precision: 0b0 ->10ns
- Phase Detector Polarity: 0b1 POSITIVE
- Power-Down (PD): 0b0 DISABLED
- Charge Pump Three-State: 0b0 DISABLED
- Counter Reset: 0b0 DISABLED
1 0 0111 0 0 1 0 0 0 010