------------------------------------------------------------------------------/
-- Description:       Simple test bench for SPI Master module
------------------------------------------------------------------------------/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SPI_rx_tb is
end entity SPI_rx_tb;

architecture TB of SPI_rx_tb is

  
  signal r_Rst_L    : std_logic := '0';
  signal r_Clk      : std_logic := '0';
  signal r_SPI_MISO : std_logic := '0';
  signal r_SPI_nCS  : std_logic := '1';
  
  -- Master Specific
  signal r_Master_CS_n     : std_logic := '1';
  signal r_Master_RX_DV    : std_logic := '0';
  signal r_Master_RX  : std_logic_vector(13 downto 0) := (others => '0');
  
begin  -- architecture TB

   -- Clock Generators:
  r_Clk <= not r_Clk after 10 ns;  -- 50 MHz -> frequency of 100 MHz

  -- Instantiate Master
  UUT : entity work.SPI_rx
    port map (
      -- Control/Data Signals,
      i_Rst_L    => r_Rst_L,            -- FPGA Reset
      i_Clk      => r_Clk,              -- FPGA Clock
      
      -- RX (MISO) Signals
      o_RX_DV    => r_Master_RX_DV,            -- Data Valid pulse
      o_RX  => r_Master_RX,          -- Byte received on MISO
      -- SPI Interface
      i_SPI_MISO => r_SPI_MISO,
      i_SPI_nCS => r_SPI_nCS
      );

  Testing : process is
  begin
  
    wait for 100 ns;
    r_Rst_L <= '0';
    wait for 100 ns;
    r_Rst_L <= '1';
    
    r_SPI_nCS <= '0';
    wait for 100 ns;
    
    r_SPI_nCS <= '1';
    wait for 140 ns;
    
    
    wait for 5000 ns;
    r_Rst_L <= '0';
    assert false report "Test Complete" severity failure;
  end process Testing;

end architecture TB;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mult_2x2_tb is

end mult_2x2_tb;

architecture Behavioral of mult_2x2_tb is
    component mult_2x2 port(
        a : in std_logic_vector (1 downto 0);
        b: in std_logic_vector (1 downto 0);
        y: out std_logic_vector (3 downto 0)
    );
    end component;
    
    -- input signals
    signal a, b: std_logic_vector (1 downto 0);
    
    --output signal
    signal y: std_logic_vector (3 downto 0);
    
    --Time interval between two test vectors
    constant DELTA : time := 10 ns;
begin
    DUT: mult_2x2 port map(
        a => a,
        b => b,
        y => y
    );
    process
        procedure send_vectors (constant in1: in natural;
                                constant in2: in natural) is
                                variable out: std_logic_vector(3 downto 0);
         begin
            --Assign values
            a <= std_logic_vector(to_unsigned(in1, a'length));
            b <= std_logic_vector(to_unsigned(in2, b'length));
            --Wait a time interval to assign the new vectors
            wait for DELTA;
            --Calculate the correct output
            mult := std_logic_vector(to_unsigned(in1 * in2, y'length));
            --Check actual output against expected result
            assert (y = mult)
            report "Wrong result: " &
                "a = " & integer'image(in1) & "; " &
                "b = " & integer'image(in2) & "; " &
                "y = " & integer'image(to_integer(unsigned(y))) & "; " &
                "y_expected = " & integer'image(to_integer(unsigned(mult))) & ";"
            severity error;
            report "TEST OK";
        end procedure send_vectors;
    begin
       send_vectors(0,0); -- 0
       send_vectors(0,1); -- 0
       send_vectors(1,0); -- 0
       send_vectors(1,1); -- 1
       send_vectors(0,2); -- 0
       send_vectors(2,0); -- 0
       send_vectors(1,2); -- 2
       send_vectors(2,1); -- 2
       send_vectors(2,2); -- 4
       send_vectors(3,0); -- 0
       send_vectors(0,3); -- 0
       send_vectors(3,1); -- 3
       send_vectors(1,3); -- 3
       send_vectors(3,2); -- 6
       send_vectors(2,3); -- 6
       send_vectors(3,3); -- 9
    end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity my_count_tb is
--  Port ( );
end my_count_tb;

architecture Behavioral of my_count_tb is
    component my_count port(
        rst : in STD_LOGIC;
        clk : in STD_LOGIC;
        en : in STD_LOGIC;
        count : out UNSIGNED (2 downto 0)
    );
    end component;

    -- input signals
    signal rst, clk, en: STD_LOGIC;

    --output signal
    signal count: UNSIGNED (2 downto 0);

    --Time interval between two test vectors
    constant clk_period : time := 1 ns;
begin
    DUT: my_count port map(
        rst => rst,
        clk => clk,
        en => en,
        count => count
    );

    process

    begin
        en <= '1';
        wait for clk_period/2;
        rst <= '0';
        wait for clk_period/2;
        rst <= '1';
        wait for clk_period/2;
        rst <= '0';
        wait for clk_period/2;
    end process;
end Behavioral;