ARCHITECTURE Behavioral OF tb_pwm IS
    COMPONENT en_4_cycles
        PORT (
            clk_12megas : IN STD_LOGIC;
            reset : IN STD_LOGIC;
            clk_3megas : OUT STD_LOGIC;
            en_2_cycles : OUT STD_LOGIC;
            en_4_cycles : OUT STD_LOGIC);
    END COMPONENT;
    
    -- Input signals
    SIGNAL clock_12megas : STD_LOGIC := '1';
    SIGNAL rst : STD_LOGIC := '0';
    SIGNAL enable_2_cycles : STD_LOGIC := '1';
    SIGNAL smpl_in : STD_LOGIC_VECTOR(sample_size - 1 DOWNTO 0);
    
    -- Output signals
    SIGNAL smpl_rqst : STD_LOGIC := '1';
    SIGNAL pwm_pls : STD_LOGIC := '1';
    SIGNAL clock_3megas : STD_LOGIC := '1';
    SIGNAL enable_4_cycles : STD_LOGIC := '1';

    -- Constant time
    CONSTANT clk_period : TIME := 83.33 ns;
    CONSTANT wait_time : TIME := 200 ns;
BEGIN
   UUT_enables : en_4_cycles
    generic map (
	  g_CLKS_PER_BIT => 67 -- 100 MHz / 1500000 Baud UART 
	)
    PORT MAP(
        clk_12megas => clock_12megas,
        reset => rst,
        clk_3megas => clock_3megas,
        en_2_cycles => enable_2_cycles,
        en_4_cycles => enable_4_cycles
    );
END Behavioral;