- Muchas notas - Fran Acién

Concurrent statements:

Modeled after hardware
Have clear, direct mapping to physical structures

Sequential statements:

Intended to describe “behavior”
Flexible and versatile
Can be difficult to be realized in hardware
Can be easily abused

Process

Process example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab2_2_1 is
   Port ( x : in STD_LOGIC_VECTOR(1 downto 0);
           y : in STD_LOGIC_VECTOR(1 downto 0);
           s : in STD_LOGIC;
           m : out STD_LOGIC_VECTOR(1 downto 0));
end lab2_2_1;

architecture Behavioral of lab2_2_1 is

begin
    -- Dataflow modeling --
    m(0) <= (x(0) and (not s)) or (y(0) and s);
    m(1) <= (x(1) and (not s)) or (y(1) and s);

    -- Conditional signal assignments --
    m <= x when s = '0' else 
    y;  -- when s = '1' 
    
    -- Selected signal assingments
    with s select m <=
    x when '0',
    y when '1';


    -- Behavioral Modeling
    p_UART_TX : process (x, y, s)
        variable tmp0: std_logic;
    begin
        tmp0 := '0';
        
        if(s = '1') then
            m <= y;
        else
            m <= x;
        end if;
    end process;
end Behavioral;

Donde x, y, y s están en la sensibility list, y cuando sufren algún cambio se ejecuta lo que hay dentro del process.

Es mejor usar señales que variables, que son más dificiles de sintetizar en hardware.

Process with wait statement

process 
begin 
    y <= a and b and c; 
    wait on a, b, c; 
end process;

Cuando no tiene sensitivity list el process continua hasta qeu encuentra un wait, que lo suspende. El wait puede tomar las siguientes formas:

wait on signals;
wait until boolean_expression;
wait for time_expression;

Process activation

Variable assignment (:=) Cambian inmediatamente dentro del process
Asignación de señales (<=) Cambian al final del process
Acaba el proceso

IF statement

if boolean_expr_1 then
    sequential_statements;
elsif boolean_expr_2 then
    sequential_statements;
elsif boolean_expr_3 then 
    sequential_statements;
. . . 
else 
    sequential_statements;
end if;

Comparison to conditional signal assignment:

Two statements are the same if there is only one output signal in if statement
If statement is more flexible
Sequential statements can be used in then, elsif and else branches:
Multiple statements
Nested if statements

Case statement

case case_expression is
    when choice_1 => sequential statements; 
    when choice\_2 => sequential statements;
    . . . 
    when others => sequential statements; 
end case;

For loop

for index in loop_range loop
    sequential statements; 
end loop;

example

process(a, b)
begin
    for i in (WIDTH-1) downto 0 loop
        y(i) <= a(i) xor b(i)
    end loop;
end process;