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20201015 - VHDL 2 - Data Types and Operations

Data types

  • integer:
    • -(2^31 -1) ↔ 2^31 -1
  • boolean: frue or false
  • bit: (‘0’, ‘1’)
  • bit_vector: one-dimension array of bit
    • bit_vector(4 downto 0)
  • character: 7-bit ASCII
  • natural: integer≥ 0
  • positive: integer > 0
  • real: Floating point, min : +1e38 to -1e38
  • string: Array of characters
  • std_logic: Substitude of bit in IEEE std_logic_1164 package
    • 9 values: (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’)
    • ‘0’, ‘1’: forcing logic 0’ and forcing logic 1
    • ‘Z’: high-impedance, as in a tri-state buffer.
    • ‘L’ , ‘H’: weak logic 0 and weak logic 1, as in wired-logic
    • ‘X’, ‘W’: “unknown” and “weak unknown”
    • ‘U’: for uninitialized
    • ‘-’: don’t-care.
  • std_logic_vector: an array of elements with std_logic data type. Imply a bus
    • signal a: std_logic_vector(7 downto o);
    • Need to invoke library ieee; use ieee.std_logic_1164.all;
  • signed and unsigned
    • signal x, y: signed(15 downto 0);
    • Need to invoke library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

Operaciones

Operator Description Data type of operand a Data type of operand b Data type of result
a ** b Exponentiation integer, signed, unsigned integer, signed, unsigned integer, signed, unsigned
abs a absolute value integer, signed integer, digned
not a negation boolean, bit, bit_vector, std_logic, std_logic_vector boolean, bit, bit_vector, std_logic, std_logic_vector
a * b multiplication integer, signed, unsigned integer, signed, unsigned integer,signed, unsigned
a / b division
a mod b modulo
a rem b remainder
+ a identity integer integer
- a negation
a + b addition integer integer integer
a - b subtraction
a & b concatenation 1-D array, element 1-D array, element 1-D array, element
a sll b shift left logical removed from IEEE 1076 bit_vector integer bit_vector
a srl b shift right logical
a sla b shift left arithmetic
a srl b shift right arithmetic
a rol b rotate left
a ror rotate right
shift_left(a, b) shift left unsigned, signed natural same as a
shift_right(a, b) shift right
rotate_left(a, b) rotate left
rotate_right(a, b) rotate right
resize(a, b) resize array unsigned, signed natural same as a
std_match(a, b) compare unsigned, signed, std_logic_vector, std_logic same as a boolean
a = b equal to any same as a booelan
a /= not equal to
a < b less than scalar or 1-D array same as a boolean
a <= b less than or equal to
a > b greater than
a >= b greater than or equal to
a and b and booelan, bit, bit_vector, std_logic, std_logic_vector same as a booelan, bit, bit_vector, std_logic, std_logic_vector
a or b or
a xor b xor
a nand b nand
a nor b nor
a xnor b xnor

Conversion

Function Data type of operand a Data type of result
to_bit(a) std_logic bit
to_stdulogic(a) bit std_logic
to_bit_vector(a) std_logic_vector bit_vector
to_stdlogicvector(a) bit_vector std_logic_vector
std_logic_vector(a) unsigned, signed std_logic_vector
unsigned(a) unsigned, std_logic_vector unsigned
to_integer(a) data type integer
to_unsigned(a, size) natural natural unsigned
to_signed(a, size) integer natura signed

Some tricky examples

Some interesting things:

y <= "00" & a(7 downto 2); 
y <= a(7) & a(7) & a(7 downto 2); 
y <= a(1 downto 0) & a(7 downto 2);

a <= "10100000"; 
a <= (7=&gt;'1', 6=>'0', 0=>'0', 1=>'0', 5=>'1', 4=>'0', 3=>'0', 2=>'1'); 
a <= (7|5=&gt;'1', 6|4|3|2|1|0=>'0'); 
a <= (7|5=&gt;'1', others=>'0');

a <= "00000000";
a <= (others=&gt;'0');