library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--*******************************
-- Ejemplo de creación de entidad
--*******************************

entity lab2_miniproj1 is
    generic (
        -- Some parameters
        OTHER_STATIC_VALUE : integer := 32
        STATIC_VALUE : integer := 32
    );
    Port ( sw : in STD_LOGIC_VECTOR(7 downto 0);
           an : out STD_LOGIC_VECTOR(7 downto 0);
           seg : out STD_LOGIC_VECTOR(6 downto 0));
end lab2_miniproj1;

architecture Behavioral of lab2_miniproj1 is

-- Declaración de Signals

signal tmp : STD_LOGIN_VECTOR(7 downto 0)
constant BUS_WIDTH: integer := 3;

begin

an <= "11111110";

seg <=
"1000000" when sw(0)='1' else
"1111001" when sw(1)='1' else
"0100100" when sw(2)='1' else
"0110000" when sw(3)='1' else
"0011001" when sw(4)='1' else
"0010010" when sw(5)='1' else
"0000010" when sw(6)='1' else
"1111000" when sw(7)='1' else
"0111111";

end Behavioral;